1. Field of the Invention
The present invention relates to a semiconductor device, and more particularly to a technique of preventing electrostatic breakdown of an input circuit.
2. Description of the Related Art
FIGS. 2A and 2B illustrate input circuits of conventional semiconductor devices. FIG. 2A shows an ordinary input circuit which is used when a level of an input signal IN is less than or equal to a power supply voltage VCC, and FIG. 2B shows an input circuit which can be used when an input signal IN is higher than a power supply voltage VCC.
The semiconductor device shown in FIG. 2A has a power supply terminal 1 connected to a power supply voltage VCC (e.g., 3.3 V), a ground terminal 2 connected to a ground voltage GND, and an input terminal 3 to which an input signal IN is input. A power supply line 4 for supplying the power supply voltage VCC into the semiconductor device is connected to the power supply terminal 1, and a ground line 5 for supplying a ground voltage GND is connected to the ground terminal 2.
An N-channel MOS transistor (hereinafter referred to as an xe2x80x9cNMOSxe2x80x9d) 6 for protection against electrostatic breakdown is connected between the input terminal 3 and the ground line 5, and a gate of this NMOS is connected to the ground line 5. Further, the input terminal 3 is connected to gates of a P-channel MOS transistor (hereinafter referred to as a xe2x80x9cPMOSxe2x80x9d) 8a and an NMOS 8b, which together form a CMOS inverter 8, via a resistor 7 for protection against an excess current. The input signal IN is inverted by the CMOS inverter 8 and is supplied to an internal circuit (not shown).
In the semiconductor device having the above-described structure, when an electrostatic surge voltage is applied to the input terminal 3 with reference to the ground terminal 2, a surge current flows from the input terminal 3 through drain and source regions of the protective NMOS 6 to the ground terminal 2, and is dissipated. When an electrostatic surge voltage is applied to the input terminal 3 with reference to the power supply terminal 1, a surge current flows from the input terminal 3 through the drain and source regions of the protective NMOS 6 to the ground line 5, and then flows via a parasitic diode 9 to the power supply terminal 1 and is dissipated. This prevents the electrostatic surge current caused by the electrostatic surge voltage applied to the input terminal 3 from flowing into the CMOS inverter 8, thereby protecting the internal circuit from electrostatic breakdown.
The semiconductor device shown in FIG. 2B has a power supply terminal 1 connected to a power supply voltage VCC (e.g., 3.3 V), a ground terminal 2 connected to a ground voltage GND, and an input terminal 3 to which an input signal IN (e.g., 5 V) is input. A power supply line 4 for supplying the power supply voltage VCC into the semiconductor device is connected to the power supply terminal 1, and a ground line 5 for supplying a ground voltage GND is connected to the ground terminal 2.
Two NMOSs 6a and 6b are connected in series between the input terminal 3 and the ground line 5. A gate of the NMOS 6a at the input terminal 3 side is connected to the power supply line 4, and a gate of the NMOS 6b at the ground line 5 side is connected to the ground line 5. Further, the input terminal 3 is connected to a transfer gate 10 via a resistor 7, and an input signal IN switched at the transfer gate 10 is supplied to an internal circuit (not shown).
In the semiconductor device shown in FIG. 2B, when an input signal IN of 5 V is input to the input terminal 3, the voltage of the input signal IN is dropped to a predetermined voltage by the resistor 7, and the signal is supplied to the internal circuit via the transfer gate 10.
The gate of the NMOS 6a is always applied with the power supply voltage of 3.3 V. Thus, a voltage (a potential difference) between drain and gate regions of the NMOS 6a will not exceed 1.7 V even when an input signal IN of 5 V is input to the input terminal 3. Further, since the drain voltage of the NMOS 6b is clamped at 3.3 minus Vth volts (Vth represents a threshold voltage of a NMOS and is usually about 0.4 V-0.6 V) by the NMOS 6a, the voltage between the drain and gate regions will not exceed the power supply voltage VCC. Therefore, since a withstand voltage of gate oxide films of the NMOSs 6a and 6b is sufficient at about 3.3 V, which is the same as that of an gate oxide film of a device forming the internal circuit, the oxide films of the NMOSs 6a and 6b can be produced by a fabrication process similar to that for the internal circuit.
However, in such conventional semiconductor devices, there has been the problem that when an input circuit is structured as shown in FIG. 2B to accommodate an input signal IN of a voltage higher than a power supply voltage VCC, the ability to protect against an electrostatic surge is inferior in comparison to a case in which the circuit shown in FIG. 2A is utilized.
That is, in FIG. 2B, when an electrostatic surge voltage is applied to the input terminal 3 with reference to the ground terminal 2, a surge current flows from the input terminal 3 through the protective NMOSs 6a and 6b to the ground terminal 2. However, a large electrostatic capacity due to the semiconductor devices exists between the ground line 5 connected to the ground terminal 2 and the power supply line 4 connected to the gate of the NMOS 6a. Therefore, the electric potential of the ground terminal 2 and the electric potential of the power supply terminal 1 alternatingly become the same, and the electrostatic surge voltage is applied to the drain-gate region of the NMOS 6a, thereby breakdown of the gate oxide film easily caused. This breakdown phenomenon becomes a more direct and serious problem when an electrostatic surge voltage is applied to the input terminal 3 with reference to the power supply terminal 1.
An object of the present invention is to solve the aforementioned problem of the prior art by providing a semiconductor device having an input circuit which can effectively prevent breakdown caused by an electrostatic surge.
In order to accomplish the above described object, a first aspect of the present invention is a semiconductor device for receiving an input signal, and power supply voltages, the semiconductor device including: an input line for receiving the input signal, first and second power supply lines for receiving power supply voltages, and an internal node; a first MOS transistor of a first conductive type, the first MOS transistor having a source electrode, a drain electrode, and a gate electrode, with the source electrode connected to the input line and the drain electrode connected to the internal node; a circuit element disposed between the first power supply line and the gate electrode of the first MOS transistor for applying a power supply voltage to the first MOS transistor gate electrode which maintains the first MOS transistor in an ON state; and a second MOS transistor of the first conductive type disposed between the second power supply line and the internal node, the second MOS transistor having a source electrode connected to the second power supply line, a drain electrode connected to the internal node, and a gate electrode connected to the second power supply line.
In a second aspect of the present invention, the circuit element in the first aspect is a third MOS transistor of a second conductive type having a gate electrode connected to the second power supply line, with the third MOS transistor being maintained in the ON state, or is a resistor element.
Operation in a semiconductor device structured as described above according to the first and the second aspects of the present invention is as follows.
When an electrostatic surge voltage is applied to the input line from outside, the electrostatic surge current flows toward the first or the second power supply line via the first and the second MOS transistors. The gate electrode of the first MOS transistor is connected to the first power supply line via the circuit element such as the third MOS transistor in the ON state or the resistor. Therefore, the electrostatic surge voltage is not directly applied to the gate electrode of the first MOS transistor.
A third aspect of the present invention is the device of the first aspect, further including a protection device connecting the gate electrode of the first MOS transistor and the internal node to one another.
A fourth aspect of the present invention is the device of the third aspect, wherein the protection device is a fourth MOS transistor of the first conductive type having a gate electrode connected to at least one of the internal node and the second power supply line, with the fourth MOS transistor being maintained in an OFF state.
Operation in the third and the fourth aspects is as follows.
When an electrostatic surge voltage is applied to the input line from outside, an electrostatic surge current flows toward the internal node via the first MOS transistor, and further toward the first or the second power supply line via the second MOS transistor. When the electrostatic surge current reaches the internal node, the protection device becomes conductive and short-circuits the gate-source region of the first MOS transistor. This prevents breakdown of the gate oxide film of the first MOS transistor caused by the electrostatic surge.
A fifth aspect of the present invention is the device of the first aspect, further including a fifth MOS transistor diode-connected in a reverse bias direction between the first and second power supply lines.
A sixth aspect of the present invention is the device of the fourth aspect, further including a fifth MOS transistor diode-connected in a reverse bias direction between the first and second power supply lines.
According to the fifth and the sixth aspects of the present invention, since the fifth MOS transistor is provided between the first and the second power supply lines and thus the first and the second power supply lines are connected by a reverse-biased diode, breakdown of a circuit due to an electrostatic surge can be prevented even in a semiconductor having an SOI (Silicon On Insulator) structure which does not have parasitic diodes.
A seventh aspect of the present invention is the device of the fourth aspect wherein impurity diffusion layers respectively corresponding to source electrodes of the first and the fourth MOS transistors are integrally formed on a semiconductor substrate. Thus, a required pattern area can be reduced.
A eighth aspect of the present invention is the device of the sixth aspect wherein impurity diffusion layers respectively corresponding to source electrodes of the first and the fourth MOS transistors are integrally formed on a semiconductor substrate; and the fourth and the fifth MOS transistors are designed so that a distance between the gate electrode and a source contact hole of the fourth MOS transistor is longer than a distance between a gate electrode and a source contact hole of the fifth MOS transistor, and a distance between the gate electrode and a drain contact hole of the fourth MOS transistor is longer than a distance between the gate electrode and a drain contact hole of the fifth MOS transistor. This makes a response from the fifth MOS transistor to an electrostatic surge faster, and therefore most of the surge current flows via this fifth MOS transistor, thereby preventing breakdown of the fourth MOS transistor.